1. Field of the Invention
The present invention relates to a solid-state image pick-up device and a pixel signal reading method of the solid-state image pick-up device.
2. Description of the Related Art
Recently, a CMOS image sensor is focused as an image sensor in place of a CCD. Because the CMOS image sensor solves such problems of the CCD that the manufacturing thereof needs a dedicated process, the operation needs a plurality of power voltages, and the operation requires the combination of a plurality of peripheral ICs to complicate the system.
The CMOS image sensor uses the same manufacturing process as that of a general worldwide produced CMOS integrated circuit (IC), and is driven by a single power-supply. Further, the CMOS image sensor mixedly includes an analog circuit and a logical circuit using the CMOS process in the same chip and therefore has a plurality of effective merits to reduce the number of peripheral ICs.
Mainly, an output circuit of the CCD uses a one-channel output with an FD (Floating Diffusion) amplifier. On the contrary, the CMOS image sensor has the FD amplifier for each pixel and mainly selects one row in a pixel array, as an output, and simultaneously reads the pixels in the column direction, that is, outputs the data in parallel with the column. Because the FD amplifier arranged in the pixel does not sufficient driving capacity, then, the reduction in data rate is necessary, and the parallel processing is advantageous.
Further, serving as another merit, since the parallel processing suppresses the band of a signal output circuit, and the noise level is thus reduced.
Various signal output circuits of the parallel-output-type CMOS image sensor are proposed. For example, the pixel output is sampled by a switching capacitor and then is read, or the pixel output is read with the amplifier arranged to each column, depending on cases, with an AD converter or a DRAM arranged to each column. The present invention particularly relates to a pixel signal reading method with an amplifier arranged to each column.
Japanese Unexamined Patent Application Publication No. 5-207220 discloses an example of the pixel signal reading method having the amplifier (e.g., single-end amplifier) arranged to each column. This will be described with reference to FIGS. 9 and 10.
FIG. 9 shows only one column corresponding to one pixel GS (circuit system of one vertical signal line VL).
The pixel GS comprises: a photodiode PD; a reset transistor Trst; an amplifying transistor Tg; and a reading transistor Ts.
In this case, an output from the pixel GS is read by using a charge integrating circuit having the capacitors C1 and C2 and a source ground amplifier 100 serving as a charge integrating amplifier. The source ground amplifier 100 comprises: a driving MOS transistor Tr16 and a load MOS transistor Tr17.
Further, in this case, the capacitor C2 serving as a feedback capacitance is pre-charged by a transistor Tr15 for switching and a reference voltage Vref. Thus, the variation in offset of the source ground amplifier 100 is suppressed.
FIG. 10 shows a timing chart of the circuit shown in FIG. 9. For a term T1 of a horizontal blanking period, the pixel GS outputs, to a vertical signal line VL, a value which is obtained by overlapping a signal Vps to an offset voltage Vo. The charge integrating circuit is reset by switching on a transistor Tr13 by a signal ARC. Similarly, the signal φRC switches on the transistor Tr15 and a signal φTC switches off a transistor Tr14, and thus the capacitor C2 pre-charges the reference voltage Vref.
For a term T2, the signals φRC and φTC switch off the transistor Tr15 and switches on the transistor Tr14, and thus the pre-charged reference voltage Vref appears at the output Vout of the charge integrating amplifier. In this case, the transistor Tr13 is switched off simultaneously with the transistor Tr15 and thus the reset state is canceled.
For a term T3, only the offset voltage Vo is outputted from the pixel GS and is integrated, thereby reading only a signal component of the output of the charge integrating amplifier using a ratio of the capacitors C1 and C2, serving as a gain.
Finally, the read signal is sequentially outputted to a horizontal signal line HL synchronously with a pulse SR supplied from a shift register 101.
In the operation for reading the pixel signal with the amplifier arranged to each column, the offset voltage of the pixel is removed and only the signal component is easily extracted. Further, the reading gain is set by the ratio of the capacitors C1 and C2. In addition, advantageously, the variation in source followers is suppressed by pre-charging the reference voltage Vref.
Another example will be described with reference to FIGS. 11, 12, and 13. This example is jointly announced as “A Column-Based Pixel-Gain-Adaptive CMOS Image Sensor for Low-Light-Level Imaging” by Shizuoka University and Sony Corporation in ISSCC (International Solid-State Circuits Conference) in 2003.
Similarly to FIG. 9, FIG. 11 shows only one column corresponding to one pixel GS (circuit system of one vertical signal line VL).
In the example shown in FIG. 11, similarly to FIG. 9, the signal from the pixel GS is read by a single-end amplifier AP and a charge integrating amplifier comprising capacitors C1 and C2.
The capacitor C2 comprises capacitors c21 and c22 and a switch Sφ3, and varies the capacitance depending on the switching-on/off operation of the switch Sφ3. Thus, the reading gain of the amplifier AP varies.
FIG. 12 shows a circuit example of the amplifier AP. Basically, the amplifier AP is a source ground amplifier comprising an N-channel MOS driving transistor T11 and a P-channel MOS current-source load transistor T10. Further, the amplifier AP has the structure of regulated cascade, that is, having cascade-connected transistors T12 and T13 and auxiliary amplifiers As1 and As2. With the structure, the excessively higher gain is obtained as compared with the source ground amplifier 100 shown in FIG. 9.
FIG. 13 shows a driving timing.
Pulses φV, φR, and φTX drive the pixel GS. Pulses φ1 to φ4 switch-on/off switches Sφ1 to Sφ4 shown in FIG. 11.
In this case, the same charge integrating amplifier is used and therefore the basic operation is similar to that shown in FIG. 9. The pixel GS shown in FIG. 11 is an example of a pixel with a transfer gate Tt and, in this case, as will be apparently understood by the driving timing shown in FIG. 13, the reset operation is performed by the pulse φR, the offset voltage Vo as the reset level is read, and then a value obtained by overlapping the signal level Vps to the offset value Vo by the pulse φTX is outputted.
This order in the example is reverse to that shown in FIG. 9. However, in the example shown in FIG. 11, a KT/C noise at the reset timing due to the pulse φR is removed and therefore the noises are reduced. The example shown in FIG. 11 recently becomes a mainstream. Incidentally, the polarity of the signal output in the example shown in FIG. 11 is inverted to that shown in FIG. 9. Further, the example shown in FIG. 11 does not include the operation for pre-recharging the reference voltage Vref, the pulse φ1 switches-on the switch Sφ1, and a signal is outputted by using a threshold voltage for feedback as the reference. The output voltage Vout is [Vt+(C1/C2)·Vps].
For example, the examples shown in FIGS. 9 and 11 are known. In the operation for reading the pixel signal with the amplifier arranged to each column as mentioned above, advantageously, the offset voltage of the pixel is removed and only the signal component is extracted without any losses. Further, the reading gain is arbitrarily set by the ratio of the capacitances.
However, the amplifier is laid-out to each column and therefore the layout area increases. The circuit structure per column must be simplified as much as possible. As described above, preferably, the relatively simple source-ground amplifier is used.
Although a differential amplifier can be used, preferably, the source ground amplifier is used in consideration of the complex circuit-structure. However, in view of PSRR (Power Supply Rejection Ratio) serving as a ratio for increasing/decreasing an input offset voltage depending on the change in power voltage, the source ground amplifier which is operated by the power supply and the ground reference deteriorates, as compared with the differential amplifier.
Here, a description is given of a specific case of a power layout pattern of the CMOS image sensor having the amplifier arranged to each column.
FIG. 14 shows a general layout-structure. Below a pixel area 200, or over and below the pixel area 200, an output circuit area 201 is arranged. In the output circuit area 201, amplifiers AP ( . . . APn, APn+1 . . . APm) are arranged to columns of vertical signal lines VL ( . . . VLn, VLn+1 . . . VLm) and therefore a large number of amplifiers AP are arranged in parallel with each other.
To each of the large number of amplifiers AP, a power supply line LVDD, a ground line LGND, or a reference signal line (not shown) of the reference voltage Vref need to be arranged. This wiring arrangement is long in parallel from PADs (power PAD and GND-PAD) on a substrate.
Then, the wiring structure becomes long and therefore the influence of a parasitic resistance r is not ignored.
In the case of using the power supply line LVDD and the ground line LGND, the current of the amplifier AP flows and therefore the influence of the parasitic resistance r causes the IR drop (voltage reduction). The potentials of power supply and ground differ between the center and the end.
Since the current flows to a line having impedance of the parasitic resistance r, the potential is always stable by setting the flowing current value to be constant. However, in the case of the source ground amplifier shown in FIG. 9, the transistor Tr17 has a transmitting conductance as the resistance and sets it as the load. Therefore, the transistor Tr17 operates like so-called resistance load and the current value flowing depending on the output value of the amplifier changes.
Referring to FIG. 12, a constant-current source is used as a load transistor T10. However, the constant-current source is limited in the voltage range of the operation as the constant-current source. An excessively-high-level signal is generated and then the output value becomes too higher. In this case, the operating area of the current source MOS transistor enters a linear area and the load transistor T10 operates like the resistance.
The operating range will be described in the case of using the current source as the load with reference to FIGS. 15A and 15B. For a brief description, the regulated cascade as shown in FIG. 12 is not used and a simple current-source as the load is used.
Referring to FIG. 15A, a voltage Vbp1 is applied to a gate of the P-channel MOS transistor T10 and an operating voltage is set within a saturated area, thereby functioning as the current source.
The load transistor T10 functions as the current source when Vout<Vbp1+Vtp (where reference symbol Vout denotes the output voltage of the amplifier and reference symbol Vtp denotes a threshold voltage of the PMOS load transistor T10). FIG. 15B shows a graph using the abscissa axis as the output voltage Vout and the ordinate axis as current Ids. When the output voltage Vout is over a value of Vbp1+Vtp, the current Ids via the amplifier reduces. Finally, when the output voltage Vout is over a value of the power voltage VDD−Vtp, the current Ids is zero.
As mentioned above, even in the case of using the load transistor T10 as the current source, the level of the pixel signal from the pixel GS is high, a high-level signal is inputted as an input voltage Vin. In this case, the output voltage Vout of the amplifier is excessively high and then the current Ids via the amplifier changes. The input signal is not so high and then the output value is soon saturated when the gain is obtained by the ratio C1/C2. Similarly, the current via the amplifier changes.
When the current value varies depending on the amount of signals, the levels of power supply and ground change, thus causing a problem that the black level changes and the change appears in the image signal.
In the examples shown in FIGS. 11 and 13, upon reading the offset signal Vo at the reset level of the pixel GS, the threshold voltage Vt needs to be not changed after that. However, the threshold voltage Vt is generated based on the power and the ground level as the reference. Therefore, when the signal is too high and the current Ids changes upon reading the signal level Vps, the levels of power supply and ground change and thus the threshold voltage Vt simultaneously changes.
As a consequence, in order to compensate for the change, the output voltage Vout of the amplifier changes and it seems that the black level changes.
More seriously, the number of amplifiers AP corresponding to the number of columns in the horizontal direction shares the impedances of the power supply and ground, the current value of any amplifier AP changes, and then the change influences on the entire amplifiers AP.
For example, strong light is partly received to the pixel area 200, the current of the amplifier AP for reading the area changes, then, the influence is shared in the horizontal direction, and the image signal having a horizontal stripe is outputted. Since the part which receives the strong light is viewed as white, the slight change in black level does not need to be considered. The part is shared with the peripheral dark portion and then the change in black level becomes the horizontal stripe and this clearly appears in the image. The appearance of stripe is a serious damage for the image sensor and becomes a problem in the case of using the single-end amplifier.
In order to solve the above-mentioned problems in the case of using the single-end amplifier of the source ground amplifier, the levels of power supply and ground need to be constant and, in any case, the current via the amplifier needs to be constant.